Careers @ Rianta Solutions

Job Description:

Junior ASIC/FPGA Design Engineer

Position will require you to use a wide range of skills and to work on some phases of the ASIC/FPGA flow.

Responsibilities include:

  • Design, implement and verify IP and modules of an ASIC or FPGA


  • Effective communication skills and a strong teamwork approach
  • 1-2 years of hands-on experience in RTL Design & Coding, Verification & Validation.
  • 1-2 years of hands-on experience using Verilog/VHDL or System Verilog.
  • Programming skills, scripting (Perl,Tcl,Csh) and C/C++ would be a plus
  • BS in Electrical Engineering
  • Familiarity with networking and processor protocols like Ethernet, PCIe, SATA, DDR, USB would be a plus
  • Skills in verification are desired