IP core

Design IP -- Verification IP -- and More

Rianta's design team has a long history of delivering full ASICs and ASSPs into production. With an average of over 20 years of design and verification experience, our team members understand the complexity and issues of using 3rd party IP within a final ASIC product. Having been on the receiving end of user-unfriendly 3rd party IP, we understand the frustration customers feel when integrating, modifying, verifying and testing IP that was packaged without a deep knowledge of customer requirements. This is why Rianta focuses on delivering complete IP blocks targeted at complex datacenter end applications.

ASIC Design IP Cores

Protocol Description Product Number
Ethernet 10/100/1000 Ethernet MAC/PCS RSm1110
Ethernet 10Gb/s Ethernet MAC RS1010
Ethernet 10Gb/s Ethernet PCS RS1011
Ethernet 40/100Gb/s Ethernet MAC/PCS RSm4100
Ethernet 400Gb/s Multi-rate (10-400G) Channelized MAC RSm400C
Ethernet 400Gb/s Multi-rate (10-400G) Channelized MAC with FlexE RSm400C_FE
MACsec MACsec security RS_MACsec

Leveraging over 100 successful ASIC/ASSP developments and associated Software and System level design experience, Rianta Solutions' team addresses key wireline, wireless, and industrial applications by developing and licensing key IP that can be ported into most processes and geometries.

We specialize in reusable RTL-based IP cores that are configured to specific technology platforms (various foundry process nodes). We partner with you to integrate the verified Design IP core with your platform.

ASIC/FPGA Verification IP

Rianta specialized in advanced, automated testbenches with self checking protocol monitors and generators. Using the latest UVM/OVM/VMM methodologies along with C++ and SystemVerilog languages, our testbenchs and verification IP support automated constrained random testing, corner case stressing, protocol complicance, porting of verification testcase to lab validation scripts, porting of lab and field debug cases to verification testcases.

Protocol Interfaces Methodologies Product Number

VIP for 1G/10/100/1G/10G/40G/100G


UVM, VMM, OVM SystemVerilog RSV40100
Ethernet VIP for switch with 10G - 100G Interfaces UVM, VMM, OVM SystemVerilog RSVxxxxTB
SDN VIP for SDN Switch UVM, VMM, OVM SystemVerilog RSV_SDN
FlexE VIP for FlexE with 5G granularity UVM, VMM, OVM SystemVerilog


Memory VIP for embedded memories UVM, VMM, OVM SystemVerilog RS_MEM
IO VIP for various CPU interfaces UVM, VMM, OVM SystemVerilog RS_IO
MACsec VIP for MACsec (100G) UVM, VMM, OVM SystemVerilog RSV_MACsec

IP Integration

With our turnkey solution offering, Rianta delivers to your custom specification. Using existing Rianta (and if necessary 3rd party IP cores), Rianta's design team designs the top level and additional custom blocks to deliver a fully verified FPGA or ASIC solution. We provide handoff options of RTL, netlist or GDSII. We can even provide you with complete software drivers and evaluation boards.

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