Verification Services

Rianta offers FPGA, ASIC and ASSP verification services performed by experienced verification engineers with an established track record of delivering complex ASICs and FPGAs. Increasing design size and complexity requires a transformation in verification strategies and methodologies for complete verification of next generation devices. Our team has more than 15 years of experience with advanced automated verification environments and has developed 6 generations of increasingly sophisticated automated verification testbenches.

Services

  • Functional Verification
  • Coverage Driven Verification
  • Constrained Random Verification
  • Assertion Based Verification
  • SystemVerilog Verification
  • Formal Verification
  • Testbench Development
  • Automated Verification Scripting

Tools:

  • System Verilog • SystemC
  • C++
  • Specman
  • OpenVera
  • UVM/OVM/VMM
  • Synopsys/Cadence/Mentor CAD tools
  • Rianta Automated Verification Tools

Design Services

Rianta’s FPGA, ASIC and ASSP design service experts can work as part of your team, providing specialized services, or we can take full ownership of a complete turnkey project. Offering both fixed price and time & materials options, Rianta has engagement models suited to our customers’ needs. Supplier issues due to unexpected last–time-buy? Need new features added to an existing FPGA or ASIC? Need a cost reduction on an existing device? Require a completely new device designed to spec? Rianta can help with design services for

Top Level Design and Simulation

  • Specification, Architecture, Design Partitioning
  • Technology Selection
  • RTL Coding in Verilog/VHDL
  • Custom IP development
  • Design for reuse, Multi-project design databases
  • Design Optimization
  • Power and Gate Count reduction strategies
  • Simulation using Verilog-XL, VCS, Verilog-NC
  • Verification environments with UVM, OVM, VMM, SystemVerilog, C++
  • Automated Design and Verification using Rianta Tools
  • Floor Planning
  • ECOs for last minute feature changes and timing closure
  • Project Management, Bug/Issue Trackers, Time Trackers, Revision Control

Synthesis, Timing Closure and Timing Analysis

  • Timing analysis and closure using Synposys, Vivado
  • Tcl, Perl scripting for constraint generation, synthesis and analysis
  • Low power optimization

Design for Testability

  • Scan, BIST, JTAG insertion and verification
  • Test wrapper creation for 3rd party IP Cores
  • ATPG vector generation, conversion and verification
  • Design for Debug
  • Built-In pattern generators and analyzers for lab, field and manufacturing test

SoC Integration and Verification

  • Integration of 3rd Party and Rianta IP Cores
  • Top level and 3rd Party IP Core verification

Redesign for Obsolete Devices or Cost Reduction

  • Cost reduction for an existing device
  • Software and pin compatible replacements
  • Second source for obsolete parts
  • Extensive experience in low-power design techniques

Verification Environment Development

Our team has more than 15 years of experience with advanced automated verification environments and has developed 6 generations of increasingly sophisticated automated verification testbenches . Taking what we have learned over 15 years from initial Verilog testbenches ( and then C and C++ testbenches), and applying these lessons to our latest UVM and SystemVerilog testbenches, Rianta offers complete, robust, automated testbenches for your ASIC or FPGA verification team.

  • Design and Development of automated testbenches
  • Verification environments with OVM, UVM, VMM, SystemVerilog, C++

Software Driver Development

Rianta specializes in building standards compliant and carrier grade embedded software drivers for custom and 3rd party FPGA, ASIC and ASSP devices. Our drivers are designed for mission critical applications (cold and warm restart, in-service upgrades) with extensive support for system debugging and integration.

  • Embedded Software Application Design and Development
  • Device Drivers for Embedded Real-Time applications
  • Networking Protocol Stacks
  • Firmware Development including BSP, boot loader and diagnostic monitor programs
  • Porting to different RTOSs
  • Software Testing (Manual and Automated)
  • Black Box Testing, White Box Testing
  • Modularity Testing
  • Automated API and documentation generation

FPGA/ASIC/ASSP Board Development

Our board designers specialize in development of evaluation and reference boards for custom FPGA/ASIC devices and standard ASSPs. Rianta’s board development experience includes:

  • Validation, Reference and Evaluation board development
  • Integrated Lab Evaluation system with RTOS and GUI support
  • Component selection
  • High speed, complex PCB design and layout
  • Clocking, Power, Datapath architecture and implementation
  • FPGA/ASIC/ASSP bring up and hardware/driver integration
  • Parametric testing and characterization

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