Verification

Rianta has more than 15 years of experience with advanced automated verification environments and has developed 6 generations of increasingly sophisticated automated verification testbenches. Our team of experienced verification engineers have an established track record of delivering complex ASICs and ASSPs. Increasing design size and complexity requires a transformation in verification strategies and methodologies for complete verification of next generation devices. .

Expertise

  • Functional Verification
  • Coverage Driven Verification
  • Constrained Random Verification
  • Assertion Based Verification
  • SystemVerilog Verification
  • Formal Verification
  • Testbench Development
  • Automated Verification Scripting

Tools:

  • UVM/OVM/VMM
  • System Verilog • SystemC
  • C++
  • Specman
  • OpenVera
  • Synopsys/Cadence/Mentor CAD tools
  • Rianta Automated Verification Tools

Design

Rianta’s ASIC and ASSP design service experts can work as part of your team, providing specialized services, or we can take full ownership of a complete turnkey project. Offering both fixed price and time & materials options, Rianta has engagement models suited to our customers’ needs. Require a completely new device designed to spec? Rianta can help with design services for

Top Level Design and Simulation

  • Specification, Architecture, Design Partitioning
  • Technology Selection
  • RTL Coding in Verilog/VHDL
  • Custom IP development
  • Design for reuse, Multi-project design databases
  • Design Optimization
  • Power and Gate Count reduction strategies
  • Simulation using Verilog-XL, VCS, Verilog-NC
  • Verification environments with UVM, OVM, VMM, SystemVerilog, C++
  • Automated Design and Verification using Rianta Tools
  • Floor Planning
  • ECOs for last minute feature changes and timing closure
  • Project Management, Bug/Issue Trackers, Time Trackers, Revision Control

Synthesis, Timing Closure and Timing Analysis

  • Timing analysis and closure using Synposys, Vivado
  • Tcl, Perl scripting for constraint generation, synthesis and analysis
  • Low power optimization

Design for Testability

  • Scan, BIST, JTAG insertion and verification
  • Test wrapper creation for 3rd party IP Cores
  • ATPG vector generation, conversion and verification
  • Design for Debug
  • Built-In pattern generators and analyzers for lab, field and manufacturing test

SoC Integration and Verification

  • Integration of 3rd Party and Rianta IP Cores
  • Top level and 3rd Party IP Core verification

Verification Environments

Our team has more than 15 years of experience with advanced automated verification environments and has developed 6 generations of increasingly sophisticated automated verification testbenches . Taking what we have learned over 15 years from initial Verilog testbenches ( and then C and C++ testbenches), and applying these lessons to our latest UVM testbenches, Rianta offers complete, robust, automated testbenches for your ASIC or FPGA verification team.

  • Design and Development of automated testbenches
  • UVM Verification environments for complex SoCs

 

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