verification functional system verilog automated testbenches asic assp strategies methodologiesExpanding design size and complexity require a transformation of verification strategies and methodologies for complete verification of next generation devices. Our expert teams have years of experience with advanced automated verification environments, and have established a reliable track record of delivering complex ASICs and ASSPs. Since its inception, Rianta has developed 6 generations of increasingly sophisticated verification testbenches.


  • Functional Verification
  • Coverage Driven Verification
  • Constrained Random Verification
  • Assertion Based Verification
  • SystemVerilog Verification
  • Formal Verification
  • Testbench Development
  • Automated Verification Scripting


  • SystemVerilog
  • Specman
  • OpenVera
  • Synopsys/Cadence/Mentor CAD Tools
  • Rianta Automated Verification Tools

Verification Environments

Rianta offers complete, robust, automated testbenches for your ASIC or FPGA verification team. Our services include:

  • Design and Development of automated testbenches
  • Verification environments with UVM, OVM, VMM, SystemVerilog for complex SoCs



verification functional system verilog automated testbenches asic assp strategies methodologiesRianta’s ASIC, ASSP, and FPGA design service experts can work as part of your team, providing specialized services, or we can take full ownership of a complete turnkey project. We have engagement models to suit your needs, including fixed price and time & materials options.
Rianta offers:

Top Level Design and Simulation

  • Specification, Architecture, Design Partitioning
  • Technology Selection
  • RTL Coding Verilog/VHDL
  • Design Optimization
  • Design for reuse, multi-project design databases
  • Power and Gate Count reduction strategies
  • Floor Planning
  • Simulation using Verilog-XL, VCS, Verilog-NC
  • ECOs for last minute feature changes and timing closure
  • Project Management, Bug/Issue Trackers, Time Trackers, Revision Control
  • Automated Design and Verification using Rianta Tools

Synthesis, Timing Closure and Timing Analysis

  • Timing analysis and closure using Synposys, Vivado
  • Tcl, Perl scripting for constraint generation, synthesis and analysis
  • Low power optimization

Design for Testability

  • Scan, BIST, JTAG insertion and verification
  • Test wrapper creation for 3rd party IP Cores
  • ATPG vector generation, conversion and verification
  • Design for Debug
  • Built-In pattern generators and analyzers for lab, field and manufacturing test

SoC Integration and Verification

  • Integration of 3rd Party and Rianta IP Cores
  • Top level and 3rd Party IP Core verification